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-rw-r--r--libraries/MultiLCD/hardware/arm/HW_ARM.h7
-rw-r--r--libraries/MultiLCD/hardware/arm/HW_ARM_defines.h40
-rw-r--r--libraries/MultiLCD/hardware/arm/HW_MX20DX256.h188
-rw-r--r--libraries/MultiLCD/hardware/arm/HW_SAM3X8E.h242
4 files changed, 477 insertions, 0 deletions
diff --git a/libraries/MultiLCD/hardware/arm/HW_ARM.h b/libraries/MultiLCD/hardware/arm/HW_ARM.h
new file mode 100644
index 0000000..c71a5ff
--- /dev/null
+++ b/libraries/MultiLCD/hardware/arm/HW_ARM.h
@@ -0,0 +1,7 @@
+void UTFT::_convert_float(char *buf, double num, int width, byte prec)
+{
+ char format[10];
+
+ sprintf(format, "%%%i.%if", width, prec);
+ sprintf(buf, format, num);
+}
diff --git a/libraries/MultiLCD/hardware/arm/HW_ARM_defines.h b/libraries/MultiLCD/hardware/arm/HW_ARM_defines.h
new file mode 100644
index 0000000..2881e17
--- /dev/null
+++ b/libraries/MultiLCD/hardware/arm/HW_ARM_defines.h
@@ -0,0 +1,40 @@
+// CTE TFT LCD/SD Shield for Arduino Due
+// -------------------------------------
+// Uncomment the following line if you are using this shield
+//#define CTE_DUE_SHIELD 1
+//
+// For this shield: RS=25, WR=26, CS=27, RST=28
+//********************************************************************
+
+// ElecHouse TFT LCD/SD Shield for Arduino Due
+// -------------------------------------
+// Uncomment the following line if you are using this shield
+//#define EHOUSE_DUE_SHIELD 1
+//
+// For this shield: RS=22, WR=23, CS=31, RST=33
+//********************************************************************
+
+// *** Hardwarespecific defines ***
+#define cbi(reg, bitmask) *reg &= ~bitmask
+#define sbi(reg, bitmask) *reg |= bitmask
+#define pulse_high(reg, bitmask) sbi(reg, bitmask); cbi(reg, bitmask);
+#define pulse_low(reg, bitmask) cbi(reg, bitmask); sbi(reg, bitmask);
+
+#define cport(port, data) port &= data
+#define sport(port, data) port |= data
+
+#define swap(type, i, j) {type t = i; i = j; j = t;}
+
+#define fontbyte(x) cfont.font[x]
+
+#define pgm_read_word(data) *data
+#define pgm_read_byte(data) *data
+#define bitmapdatatype unsigned short*
+
+#if defined(TEENSYDUINO) && TEENSYDUINO >= 117
+ #define regtype volatile uint8_t
+ #define regsize uint8_t
+#else
+ #define regtype volatile uint32_t
+ #define regsize uint32_t
+#endif
diff --git a/libraries/MultiLCD/hardware/arm/HW_MX20DX256.h b/libraries/MultiLCD/hardware/arm/HW_MX20DX256.h
new file mode 100644
index 0000000..93df980
--- /dev/null
+++ b/libraries/MultiLCD/hardware/arm/HW_MX20DX256.h
@@ -0,0 +1,188 @@
+/**
+ *
+ * This file is a modified version of the HW_Teensy3.h created by Paul Stoffregen.
+ *
+ * Teensy 3.x pin definitions created by Dawnmist
+ * http://forum.pjrc.com/threads/18002-Teensy-3-0-driving-an-SSD1289-with-utft?p=34719&viewfull=1#post34719
+ *
+ * This file only supports the B and D ports as defined by Dawnmist for 8-bit and 16-bit display modules.
+ * Serial display modules are also supported.
+ *
+ * NOTE: This file has only been tested on a Teensy 3.1
+ *
+**/
+
+// *** Hardware specific functions ***
+void UTFT::_hw_special_init()
+{
+}
+
+void UTFT::LCD_Writ_Bus(char VH,char VL, byte mode)
+{
+ switch (mode)
+ {
+ case 1:
+ if (display_serial_mode==SERIAL_4PIN)
+ {
+ if (VH==1)
+ sbi(P_SDA, B_SDA);
+ else
+ cbi(P_SDA, B_SDA);
+ pulse_low(P_SCL, B_SCL);
+ }
+ else
+ {
+ if (VH==1)
+ sbi(P_RS, B_RS);
+ else
+ cbi(P_RS, B_RS);
+ }
+
+ if (VL & 0x80)
+ sbi(P_SDA, B_SDA);
+ else
+ cbi(P_SDA, B_SDA);
+ pulse_low(P_SCL, B_SCL);
+ if (VL & 0x40)
+ sbi(P_SDA, B_SDA);
+ else
+ cbi(P_SDA, B_SDA);
+ pulse_low(P_SCL, B_SCL);
+ if (VL & 0x20)
+ sbi(P_SDA, B_SDA);
+ else
+ cbi(P_SDA, B_SDA);
+ pulse_low(P_SCL, B_SCL);
+ if (VL & 0x10)
+ sbi(P_SDA, B_SDA);
+ else
+ cbi(P_SDA, B_SDA);
+ pulse_low(P_SCL, B_SCL);
+ if (VL & 0x08)
+ sbi(P_SDA, B_SDA);
+ else
+ cbi(P_SDA, B_SDA);
+ pulse_low(P_SCL, B_SCL);
+ if (VL & 0x04)
+ sbi(P_SDA, B_SDA);
+ else
+ cbi(P_SDA, B_SDA);
+ pulse_low(P_SCL, B_SCL);
+ if (VL & 0x02)
+ sbi(P_SDA, B_SDA);
+ else
+ cbi(P_SDA, B_SDA);
+ pulse_low(P_SCL, B_SCL);
+ if (VL & 0x01)
+ sbi(P_SDA, B_SDA);
+ else
+ cbi(P_SDA, B_SDA);
+ pulse_low(P_SCL, B_SCL);
+ break;
+ case 8:
+ *(volatile uint8_t *)(&GPIOD_PDOR) = VH;
+ pulse_low(P_WR, B_WR);
+ *(volatile uint8_t *)(&GPIOD_PDOR) = VL;
+ pulse_low(P_WR, B_WR);
+ break;
+ case 16:
+ *(volatile uint8_t *)(&GPIOD_PDOR) = VH;
+ GPIOB_PCOR = 0x000F000F; // clear data lines B0-3,B16-19
+ GPIOB_PSOR = (0x0F & VL) | ((VL >> 4) << 16); // set data lines 0-3,16-19 if set in cl
+ pulse_low(P_WR, B_WR);
+ break;
+ }
+}
+
+void UTFT::_set_direction_registers(byte mode)
+{
+ GPIOD_PDDR |= 0xFF;
+ PORTD_PCR0 = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(1);
+ PORTD_PCR1 = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(1);
+ PORTD_PCR2 = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(1);
+ PORTD_PCR3 = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(1);
+ PORTD_PCR4 = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(1);
+ PORTD_PCR5 = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(1);
+ PORTD_PCR6 = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(1);
+ PORTD_PCR7 = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(1);
+
+ if (mode == 16)
+ {
+ GPIOB_PDDR |= 0x000F000F;
+ PORTB_PCR0 = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(1);
+ PORTB_PCR1 = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(1);
+ PORTB_PCR2 = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(1);
+ PORTB_PCR3 = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(1);
+ PORTB_PCR16 = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(1);
+ PORTB_PCR17 = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(1);
+ PORTB_PCR18 = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(1);
+ PORTB_PCR19 = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(1);
+ }
+}
+void UTFT::_fast_fill_16(int ch, int cl, long pix)
+{
+ long blocks;
+
+ *(volatile uint8_t *)(&GPIOD_PDOR) = ch;
+ GPIOB_PCOR = 0x000F000F; // clear data lines B0-3,B16-19
+ GPIOB_PSOR = (0x0F & cl) | ((cl >> 4) << 16); // set data lines 0-3,16-19 if set in cl
+
+ blocks = pix/16;
+ for (int i=0; i<blocks; i++)
+ {
+ pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);
+ }
+ if ((pix % 16) != 0)
+ for (int i=0; i<(pix % 16); i++)
+ {
+ pulse_low(P_WR, B_WR);
+ }
+}
+
+void UTFT::_fast_fill_8(int ch, long pix)
+{
+ long blocks;
+
+ *(volatile uint8_t *)(&GPIOD_PDOR) = ch;
+
+ blocks = pix/16;
+ for (int i=0; i<blocks; i++)
+ {
+ pulse_low(P_WR, B_WR);pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);pulse_low(P_WR, B_WR);
+ }
+ if ((pix % 16) != 0)
+ for (int i=0; i<(pix % 16); i++)
+ {
+ pulse_low(P_WR, B_WR);pulse_low(P_WR, B_WR);
+ }
+}
diff --git a/libraries/MultiLCD/hardware/arm/HW_SAM3X8E.h b/libraries/MultiLCD/hardware/arm/HW_SAM3X8E.h
new file mode 100644
index 0000000..f4ac4ab
--- /dev/null
+++ b/libraries/MultiLCD/hardware/arm/HW_SAM3X8E.h
@@ -0,0 +1,242 @@
+// *** Hardwarespecific functions ***
+void UTFT::_hw_special_init()
+{
+#ifdef EHOUSE_DUE_SHIELD
+ pinMode(24, OUTPUT); digitalWrite(24, HIGH); // Set the TFT_RD pin permanently HIGH as it is not supported by UTFT
+#endif
+}
+
+void UTFT::LCD_Writ_Bus(char VH,char VL, byte mode)
+{
+ switch (mode)
+ {
+ case 1:
+ if (display_serial_mode==SERIAL_4PIN)
+ {
+ if (VH==1)
+ sbi(P_SDA, B_SDA);
+ else
+ cbi(P_SDA, B_SDA);
+ pulse_low(P_SCL, B_SCL);
+ }
+ else
+ {
+ if (VH==1)
+ sbi(P_RS, B_RS);
+ else
+ cbi(P_RS, B_RS);
+ }
+
+ if (VL & 0x80)
+ sbi(P_SDA, B_SDA);
+ else
+ cbi(P_SDA, B_SDA);
+ pulse_low(P_SCL, B_SCL);
+ if (VL & 0x40)
+ sbi(P_SDA, B_SDA);
+ else
+ cbi(P_SDA, B_SDA);
+ pulse_low(P_SCL, B_SCL);
+ if (VL & 0x20)
+ sbi(P_SDA, B_SDA);
+ else
+ cbi(P_SDA, B_SDA);
+ pulse_low(P_SCL, B_SCL);
+ if (VL & 0x10)
+ sbi(P_SDA, B_SDA);
+ else
+ cbi(P_SDA, B_SDA);
+ pulse_low(P_SCL, B_SCL);
+ if (VL & 0x08)
+ sbi(P_SDA, B_SDA);
+ else
+ cbi(P_SDA, B_SDA);
+ pulse_low(P_SCL, B_SCL);
+ if (VL & 0x04)
+ sbi(P_SDA, B_SDA);
+ else
+ cbi(P_SDA, B_SDA);
+ pulse_low(P_SCL, B_SCL);
+ if (VL & 0x02)
+ sbi(P_SDA, B_SDA);
+ else
+ cbi(P_SDA, B_SDA);
+ pulse_low(P_SCL, B_SCL);
+ if (VL & 0x01)
+ sbi(P_SDA, B_SDA);
+ else
+ cbi(P_SDA, B_SDA);
+ pulse_low(P_SCL, B_SCL);
+ break;
+ case 8:
+#if defined(CTE_DUE_SHIELD) || defined(EHOUSE_DUE_SHIELD)
+ REG_PIOC_CODR=0xFF000;
+ REG_PIOC_SODR=(VH<<12) & 0xFF000;
+ pulse_low(P_WR, B_WR);
+ REG_PIOC_CODR=0xFF000;
+ REG_PIOC_SODR=(VL<<12) & 0xFF000;
+ pulse_low(P_WR, B_WR);
+#else
+ REG_PIOA_CODR=0x0000C000;
+ REG_PIOD_CODR=0x0000064F;
+ REG_PIOA_SODR=(VH & 0x06)<<13;
+ (VH & 0x01) ? REG_PIOB_SODR = 0x4000000 : REG_PIOB_CODR = 0x4000000;
+ REG_PIOD_SODR=((VH & 0x78)>>3) | ((VH & 0x80)>>1);
+ pulse_low(P_WR, B_WR);
+
+ REG_PIOA_CODR=0x0000C000;
+ REG_PIOD_CODR=0x0000064F;
+ REG_PIOA_SODR=(VL & 0x06)<<13;
+ (VL & 0x01) ? REG_PIOB_SODR = 0x4000000 : REG_PIOB_CODR = 0x4000000;
+ REG_PIOD_SODR=((VL & 0x78)>>3) | ((VL & 0x80)>>1);
+ pulse_low(P_WR, B_WR);
+#endif
+ break;
+ case 16:
+#if defined(CTE_DUE_SHIELD)
+ REG_PIOC_CODR=0xFF1FE;
+ REG_PIOC_SODR=(VL<<1) & 0x1FE;
+ REG_PIOC_SODR=(VH<<12) & 0xFF000;
+#elif defined(EHOUSE_DUE_SHIELD)
+ PIOC->PIO_ODSR = ((PIOC->PIO_ODSR&(~0x000FF3FC)) | ((((uint32_t)VL)<<2) | (((uint32_t)VH)<<12)));
+#else
+ REG_PIOA_CODR=0x0000C080;
+ REG_PIOC_CODR=0x0000003E;
+ REG_PIOD_CODR=0x0000064F;
+ REG_PIOA_SODR=((VH & 0x06)<<13) | ((VL & 0x40)<<1);
+ (VH & 0x01) ? REG_PIOB_SODR = 0x4000000 : REG_PIOB_CODR = 0x4000000;
+ REG_PIOC_SODR=((VL & 0x01)<<5) | ((VL & 0x02)<<3) | ((VL & 0x04)<<1) | ((VL & 0x08)>>1) | ((VL & 0x10)>>3);
+ REG_PIOD_SODR=((VH & 0x78)>>3) | ((VH & 0x80)>>1) | ((VL & 0x20)<<5) | ((VL & 0x80)<<2);
+#endif
+ pulse_low(P_WR, B_WR);
+ break;
+ case LATCHED_16:
+ asm("nop"); // Mode is unsupported
+ break;
+ }
+}
+
+void UTFT::_set_direction_registers(byte mode)
+{
+ if (mode!=LATCHED_16)
+ {
+#if defined(CTE_DUE_SHIELD)
+ if (mode==16)
+ {
+ REG_PIOC_OER=0x000FF1FE;
+ }
+ else
+ REG_PIOC_OER=0x000FF000;
+#elif defined(EHOUSE_DUE_SHIELD)
+ if (mode==16)
+ {
+ REG_PIOC_OER=0x000FF3FC;
+ REG_PIOC_OWER=0x000FF3FC;
+ }
+ else
+ REG_PIOC_OER=0x000FF000;
+#else
+ REG_PIOA_OER=0x0000c000; //PA14,PA15 enable
+ REG_PIOB_OER=0x04000000; //PB26 enable
+ REG_PIOD_OER=0x0000064f; //PD0-3,PD6,PD9-10 enable
+ if (mode==16)
+ {
+ REG_PIOA_OER=0x00000080; //PA7 enable
+ REG_PIOC_OER=0x0000003e; //PC1 - PC5 enable
+ }
+#endif
+ }
+ else
+ {
+ asm("nop"); // Mode is unsupported
+ }
+}
+
+void UTFT::_fast_fill_16(int ch, int cl, long pix)
+{
+ long blocks;
+
+#if defined(CTE_DUE_SHIELD)
+ REG_PIOC_CODR=0xFF1FE;
+ REG_PIOC_SODR=(cl<<1) & 0x1FE;
+ REG_PIOC_SODR=(ch<<12) & 0xFF000;
+#elif defined(EHOUSE_DUE_SHIELD)
+ PIOC->PIO_ODSR = ((PIOC->PIO_ODSR&(~0x000FF3FC)) | ((((uint32_t)cl)<<2) | (((uint32_t)ch)<<12)));
+#else
+ REG_PIOA_CODR=0x0000C080;
+ REG_PIOC_CODR=0x0000003E;
+ REG_PIOD_CODR=0x0000064F;
+ REG_PIOA_SODR=((ch & 0x06)<<13) | ((cl & 0x40)<<1);
+ (ch & 0x01) ? REG_PIOB_SODR = 0x4000000 : REG_PIOB_CODR = 0x4000000;
+ REG_PIOC_SODR=((cl & 0x01)<<5) | ((cl & 0x02)<<3) | ((cl & 0x04)<<1) | ((cl & 0x08)>>1) | ((cl & 0x10)>>3);
+ REG_PIOD_SODR=((ch & 0x78)>>3) | ((ch & 0x80)>>1) | ((cl & 0x20)<<5) | ((cl & 0x80)<<2);
+#endif
+
+ blocks = pix/16;
+ for (int i=0; i<blocks; i++)
+ {
+ pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);
+ }
+ if ((pix % 16) != 0)
+ for (int i=0; i<(pix % 16)+1; i++)
+ {
+ pulse_low(P_WR, B_WR);
+ }
+}
+
+void UTFT::_fast_fill_8(int ch, long pix)
+{
+ long blocks;
+
+#if defined(CTE_DUE_SHIELD) || defined(EHOUSE_DUE_SHIELD)
+ REG_PIOC_CODR=0xFF000;
+ REG_PIOC_SODR=(ch<<12) & 0xFF000;
+#else
+ REG_PIOA_CODR=0x0000C000;
+ REG_PIOD_CODR=0x0000064F;
+ REG_PIOA_SODR=(ch & 0x06)<<13;
+ (ch & 0x01) ? REG_PIOB_SODR = 0x4000000 : REG_PIOB_CODR = 0x4000000;
+ REG_PIOD_SODR=((ch & 0x78)>>3) | ((ch & 0x80)>>1);
+#endif
+
+ blocks = pix/16;
+ for (int i=0; i<blocks; i++)
+ {
+ pulse_low(P_WR, B_WR);pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);pulse_low(P_WR, B_WR);
+ pulse_low(P_WR, B_WR);pulse_low(P_WR, B_WR);
+ }
+ if ((pix % 16) != 0)
+ for (int i=0; i<(pix % 16)+1; i++)
+ {
+ pulse_low(P_WR, B_WR);pulse_low(P_WR, B_WR);
+ }
+}
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